Method and apparatus for comparing programmable logic device configurations
US8161469B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 13, 2005 |
| Grant date | Apr 17, 2012 |
| Priority date | — |
| Expiry date | Mar 18, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Compiled configuration files for different programmable logic devices that are intended to be functionally equivalent may be compared using multiple different comparisons to assure functional equivalence. The different comparisons include a fitter or resource report comparison, an engineering bit settings report that compares vectors of bits that represent the settings of hard logic blocks, and comparisons based on location, connectivity and functionality. These comparisons are particularly well-suited for determining equivalence between different models of programmable logic devices, or even different types of devices such as field-programmable gate arrays as compared to mask-programmable logic devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.