Fabrication of semiconductor structure having asymmetric field-effect transistor with tailored pocket portion along source/drain zone
US8163619B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 27, 2009 |
| Grant date | Apr 24, 2012 |
| Priority date | — |
| Expiry date | Aug 22, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/314
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An asymmetric insulated-gate field effect transistor (100U or 102U) is provided along an upper surface of a semiconductor body so as to have first and second source/drain zones (240 and 242 or 280 and 282) laterally separated by a channel zone (244 or 284) of the transistor's body material. A gate electrode (262 or 302) overlies a gate dielectric layer (260 or 300) above the channel zone. A pocket portion (250 or 290) of the body material more heavily doped than laterally adjacent material of the body material extends along largely only the first of the S/D zones and into the channel zone. The vertical dopant profile of the pocket portion is tailored to reach a plurality of local maxima at respective locations (PH-1-PH-3-NH-3) spaced apart from one another. This typically enables the transistor to have reduced current leakage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.