Device and technique for transistor well biasing
US8164378B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 6, 2008 |
| Grant date | Apr 24, 2012 |
| Priority date | — |
| Expiry date | Jan 26, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0018
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A method includes receiving a set of voltages comprising at least a first voltage, a second voltage, and a third voltage and biasing a well of a transistor based on the extreme voltage of the set of voltages. Biasing the well of the transistor can include concurrently providing a first signal and a second signal based on a comparison of the first voltage and the second voltage and selectively coupling the well of the transistor to a source of the extreme voltage of the set of voltages based on the first signal, the second signal, and the third voltage. An electronic device comprises a transistor and a power switching module. The power switching module includes a set of inputs, each input configured to receive a corresponding one of a set of voltages comprising at least a first voltage, a second voltage, and a third voltage, and includes an output coupled to a well of the transistor, the output configured to provide the extreme voltage of the set of voltages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.