Address decoder
US8164972B1 · kind B1 · utility
11Cited by
11References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 6, 2010 |
| Grant date | Apr 24, 2012 |
| Priority date | — |
| Expiry date | Dec 6, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An address decoder that includes a plurality of predecoders configured to (i) receive and logically combine a clock signal and address signals and (ii) generate addresses and complementary addresses. At least one of the plurality of precoders includes a first logic gate configured to receive the clock signal and one of the address signals, and a second logic gate configured to receive the clock signal and an output of the first logic gate. The address decoder further includes a decoder configured to generate a decoder output based on the addresses and complementary addresses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.