Three-dimensional semiconductor template for making high efficiency thin-film solar cells
US8168465B2 · kind B2 · utility
13Cited by
65References
5Claims
0Family size
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Key dates
| Filing date | Nov 13, 2009 |
| Grant date | May 1, 2012 |
| Priority date | — |
| Expiry date | Jan 6, 2030 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T117/1092
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor template having a top surface aligned along a (100) crystallographic orientation plane and an inverted pyramidal cavity defined by a plurality of walls aligned along a (111) crystallographic orientation plane. A method for manufacturing a semiconductor template by selectively removing silicon material from a silicon template to form a top surface aligned along a (100) crystallographic plane of the silicon template and a plurality of walls defining an inverted pyramidal cavity each aligned along a (111) crystallographic plane of the silicon template.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.