Double gate depletion mode MOSFET
US8168500B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 25, 2011 |
| Grant date | May 1, 2012 |
| Priority date | — |
| Expiry date | Jan 25, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/125
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A metal-oxide-semiconductor field effect transistor (MOSFET) has a body layer that follows the contour of exposed surfaces of a semiconductor substrate and contains a bottom surface of a shallow trench and adjoined sidewalls. A bottom electrode layer vertically abuts the body layer and provides an electrical bias to the body layer. A top electrode and source and drain regions are formed on the body layer. The thickness of the body layer is selected to allow full depletion of the body layer by the top electrode and a bottom electrode layer. The portion of the body layer underneath the shallow trench extends the length of a channel to enable a high voltage operation. Further, the MOSFET provides a double gate configuration and a tight control of the channel to enable a complete pinch-off of the channel and a low off-current in a compact volume.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.