Semiconductor memory device and production method thereof

US8169030B2 · kind B2 · utility

Assignee

• UNISANTIS ELECTRONICS SINGAPORE PTE. LTD. · SG

Inventors

• Fujio Masuoka · Yokohama, JP
• Shintaro Arai · Tokyo, JP

Key dates

• Filing date: Sep 14, 2010
• Grant date: May 1, 2012
• Expiry date: Jan 1, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/038

Abstract

In a static memory cell composed of four MOS transistors, the transistors composing a memory cell are formed on a substrate and have a drain, gate, and source arranged vertically with the gate surrounding a columnar semiconductor layer. In this memory cell, the first diffusion layers (second diffusion layers) functioning as a first memory node (second memory node) are connected via a first silicide layer (second silicide layer) formed on their surfaces, whereby an SRAM cell having a small area is realized. Furthermore, a first anti-leak diffusion layer (second anti-leak diffusion layer) having the conductivity type opposite to the first well is formed between the first well and the first diffusion layer (second diffusion layer) having the same conductivity type as the first well so as to prevent leak to the substrate.