Low profile ball grid array (BGA) package with exposed die and method of making same
US8169067B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 20, 2006 |
| Grant date | May 1, 2012 |
| Priority date | — |
| Expiry date | Sep 8, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/351
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods and apparatuses for improved thermal, electrical and/or mechanical performance in integrated circuit (IC) packages are described. An IC circuit package comprises a substrate having a central opening. An IC die, resides within the opening in the substrate. Wirebonds couples a plurality of bond pads on a top surface of the IC die to a plurality of bond fingers on a top surface the substrate. An encapsulating material encapsulates at least the IC die and the wirebonds such that at least a bottom surface of the IC die is left exposed. The encapsulating material suspends the die such that at least a portion of the die is held within the opening in the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.