Semiconductor device having vertically offset bond on trace interconnects on recessed and raised bond fingers
US8169071B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 2, 2011 |
| Grant date | May 1, 2012 |
| Priority date | — |
| Expiry date | Feb 2, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/1476
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a substrate, a first recessed conductive layer embedded and recessed into a first surface of the substrate, and a first raised conductive layer disposed above the first surface. A first vertical offset exists between an upper surface of the first recessed conductive layer and an upper surface of the first raised conductive layer. The device includes a second recessed conductive layer embedded and recessed into a second surface of the substrate. The second surface of the substrate is opposite the first surface. The device includes a second raised conductive layer disposed beneath the second surface and an interconnect structure disposed on the first recessed and raised conductive layers and the second recessed and raised conductive layers. A second vertical offset exists between a lower surface of the second recessed conductive layer and a lower surface of the second recessed conductive layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.