Test method using memory programmed with tests and protocol to communicate between device under test and tester
US8170828B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 5, 2009 |
| Grant date | May 1, 2012 |
| Priority date | — |
| Expiry date | Apr 17, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31726
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
In an embodiment, a test method is implemented to test an integrated circuit that includes at least one processor. The method may include programming a memory to which the integrated circuit is coupled during testing with one or more test programs. The integrated circuit may be booted, and the processor may execute the test programs from the memory. In one embodiment, the memory may also store a control program that may manage the execution of the tests. In an embodiment, the control program may also implement a protocol to communicate with the ATE to perform the testing. The protocol may be implemented over a set of general purpose input/output (I/O) pins, for example. Using the protocol and test vectors on the ATE, the tests may be selected and executed, and test results may be reported.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.