In-situ design method and system for improved memory yield
US8170857B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 26, 2008 |
| Grant date | May 1, 2012 |
| Priority date | — |
| Expiry date | Aug 15, 2030 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P90/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for designing integrated circuits includes determining a target memory module for evaluation and improvement by evaluating performance variables of the memory module. The performance variables are statistically simulated over subset combinations of variables based on pin information for the module. Sensitivities of performance on yield to the variables in the subset combinations are determined. It is then determined whether yield of the target module is acceptable, and if the yield is not acceptable, a design which includes the target module is adjusted in accordance with the sensitivities to adjust the yield.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.