Wafer with scribe lanes comprising external pads and/or active circuits for die testing
US8173448B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 25, 2006 |
| Grant date | May 8, 2012 |
| Priority date | — |
| Expiry date | Apr 11, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A wafer comprises i) at least one independent die having internal integrated components, a multiplicity of internal pads connected to some of the internal integrated components, ii) scribe lanes defined between and around each independent die, and in part of which are defined, for each die, at least a first group of external pads and/or a second group of external test integrated components. The external pads of each first group are connected, through conductive tracks, to a chosen one of the internal pads and/or internal integrated components of the associated die, and arranged to be fed with chosen test signals or to collect test result signals. Each external test integrated components of each second group is connected, through conductive tracks, to a chosen one of the die internal pads and/or die internal integrated components and/or to external pads of a first group.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.