Gate-all-around nanowire tunnel field effect transistors
US8173993B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 4, 2009 |
| Grant date | May 8, 2012 |
| Priority date | — |
| Expiry date | Nov 4, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/85
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A method for forming a nanowire tunnel field effect transistor (FET) device includes forming a nanowire suspended by first and second pad regions over a semiconductor substrate, the nanowire including a core portion and a dielectric layer, forming a gate structure around a portion of the dielectric layer, forming a first spacer around portions of the nanowire extending from the gate structure, implanting ions in a first portion of the nanowire, implanting ions in the dielectric layer of a second portion of the nanowire, removing the dielectric layer from the second portion of the nanowire, removing the core portion of the second portion of the exposed nanowire to form a cavity, and epitaxially growing a doped semiconductor material in the cavity from exposed cross sections of the nanowire and the second pad region to connect the exposed cross sections of the nanowire to the second pad region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.