Dummy pattern in wafer backside routing
US8174124B2 · kind B2 · utility
31Cited by
41References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 8, 2010 |
| Grant date | May 8, 2012 |
| Priority date | — |
| Expiry date | Aug 27, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A device includes a semiconductor substrate including a front side and a backside. A through-substrate via (TSV) penetrates the semiconductor substrate. A dummy metal line is formed on the backside of the semiconductor substrate, and may be connected to the dummy TSV.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.