Techniques for reducing disturbance in a semiconductor device
US8174881B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 24, 2009 |
| Grant date | May 8, 2012 |
| Priority date | — |
| Expiry date | Feb 2, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques for reducing disturbance in a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device having reduced disturbance. The semiconductor memory device may comprise a plurality of memory cells arranged in arrays of rows and columns. The semiconductor memory device may also comprise a plurality of data sense amplifiers, coupled to the plurality of memory cells, configured to perform one or more operations during an operation/access cycle, wherein the operation/access cycle may comprise an operation segment and a disturbance recovery segment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.