High speed operation method for twin MONOS metal bit array
US8174885B2 · kind B2 · utility
0Cited by
18References
22Claims
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Key dates
| Filing date | May 2, 2011 |
| Grant date | May 8, 2012 |
| Priority date | — |
| Expiry date | May 2, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0475
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a novel read method of twin MONOS metal bit or diffusion bit structure for high-speed application. In a first embodiment of the present invention, the alternative control gates are set at the same voltage. In a second embodiment of the present invention, all the control gates are set at the operational voltage from the beginning. In both embodiments, the bit line and word gate are used to address the selected memory cell.teh
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.