Patent · US Active

Encryption apparatus with diverse key retention schemes

US8175276B2 · kind B2 · utility

14Cited by

11References

20Claims

0Family size

Assignee

Freeescale Semiconductor, Inc. · US

Inventors

Thomas E. Tkacik · Phoenix, US
Asaf Ashkenazi · Haifa, IL

Key dates

Filing date	Feb 4, 2008
Grant date	May 8, 2012
Priority date	—
Expiry date	Jan 4, 2031

Classification

Technology area (CPC H)Electricity
CPC primaryH04L2209/12
WIPO fieldDigital communication
WIPO sectorElectrical engineering

Abstract

An encryption apparatus (14) includes a secure processing system (12) in the form of an integrated circuit. The secure processing system (12) includes an on-chip secure memory system (30). The secure memory system (30) includes a non-volatile, read-only, permanent key register (62) in which a permanent cryptographic key (64) is stored. The secure memory system (30) also includes a non-volatile, read-write, erasable key register (56) in which an erasable cryptographic key (60) is stored. Symmetric cryptographic operations take place in an encryption engine (46) using an operating cryptographic key (68) formed by combining (96) the permanent and erasable keys (64, 60). A tamper detection circuit (70) detects tampering and erases the erasable key (60) when a tamper event is detected.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.