Buffer management architecture
US8176291B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 10, 2010 |
| Grant date | May 8, 2012 |
| Priority date | — |
| Expiry date | Mar 10, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/023
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and apparatus for managing buffers in a buffer memory are described. In at least one aspect, a system includes a buffer memory including a plurality of buffers; an allocation memory including a plurality of allocation data elements associated with the plurality of buffers; an allocation clear register coupled with the allocation memory; a reclaim memory including a plurality of reclaim data elements each associated with an allocation data element and corresponding buffer; a reclaim clear register coupled with the reclaim memory; an allocation register configured to receive one or more allocation data elements from the allocation memory; and a buffer manager.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.