Wave pipeline with selectively opaque register stages
US8176354B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 25, 2010 |
| Grant date | May 8, 2012 |
| Priority date | — |
| Expiry date | Oct 19, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/3888
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A selectively synchronous wave pipeline segment and an integrated circuit (IC) including the segment. The segment includes a normally opaque input stage and output stage and multiple internal stages that are normally transparent. A programmable local clock control circuit provides internal stage clock selection control to internal stages. The internal clock selection control determines whether each internal pipeline stage is gated opaque by a local clock. The programmable local clock control circuit is programmed to allows data items to propagate as data waves in a wave pipeline until each wave reaches a point where beyond, a race condition is likely to exist. Multiple pipeline data items pass as data waves between input and said output stage selectively unclocked.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.