Online multiprocessor system reliability defect testing
US8176362B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 24, 2008 |
| Grant date | May 8, 2012 |
| Priority date | — |
| Expiry date | Mar 9, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3409
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiprocessor system comprising a plurality of processors is disclosed. The plurality of processors includes a first processor including first monitor on-chip and a second processor including a including a second monitor on-chip. The first monitor on-chip is configured to measure load on the second processor and the second monitor on-chip is configured to measure load on the first processor. The first monitor on-chip is configured to cause the second monitor on-chip to perform a self-test on the second processor if the load on the second processor is below a second processor load threshold value and the second monitor on-chip is configured to cause the first monitor on-chip to perform a self-test on the first processor if the load on the first processor is below first processor load threshold value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.