Vikram Iyengar
26Patents
6h-index
30Co-inventors
65Inventor score
Filing activity: Feb 28, 2006 → Apr 3, 2018
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7620921B2 | IC chip at-functional-speed testing with process coverage evaluation | Physics | 23 | Active |
| US9104834B2 | Systems and methods for single cell product path delay analysis | Physics | 20 | Active |
| US8543966B2 | Test path selection and test program generation for performance testing integrated circuit chips | Physics | 8 | Active |
| US8209141B2 | System and method for automatically generating test patterns for at-speed structural test of an integrated circuit device using an incremental approach to reduce test pattern count | Physics | 7 | Active |
| US7996807B2 | Integrated test waveform generator (TWG) and customer waveform generator (CWG), design structure and method | Physics | 7 | Active |
| US7856607B2 | System and method for generating at-speed structural tests to improve process and environmental parameter space coverage | Physics | 7 | Active |
| US9058034B2 | Integrated circuit product yield optimization using the results of performance path testing | Emerging Cross-Sectional Technologies | 5 | Active |
| US7721170B2 | Apparatus and method for selectively implementing launch off scan capability in at speed testing | Physics | 5 | Active |
| US8230283B2 | Method to test hold path faults using functional clocking | Physics | 5 | Active |
| US10424821B2 | Thermally regulated modular energy storage device and methods | Emerging Cross-Sectional Technologies | 4 | Active |
| US7779375B2 | Design structure for shutting off data capture across asynchronous clock domains during at-speed testing | Physics | 3 | Active |
| US7441171B2 | Efficient scan chain insertion using broadcast scan for reduced bit collisions | Physics | 3 | Active |
| US7685542B2 | Method and apparatus for shutting off data capture across asynchronous clock domains during at-speed testing | Physics | 3 | Active |
| US7529294B2 | Testing of multiple asynchronous logic domains | Physics | 2 | Active |
| US8539429B1 | System yield optimization using the results of integrated circuit chip performance path testing | Physics | 2 | Active |
| US9557378B2 | Method and structure for multi-core chip product test and selective voltage binning disposition | Physics | 2 | Active |
| US8538718B2 | Clock edge grouping for at-speed test | Physics | 2 | Active |
| US8490040B2 | Disposition of integrated circuits using performance sort ring oscillator and performance path testing | Physics | 2 | Active |
| US8825433B2 | Automatic generation of valid at-speed structural test (ASST) test groups | Physics | 1 | Active |
| US8176362B2 | Online multiprocessor system reliability defect testing | Physics | 1 | Active |
| US8181135B2 | Hold transition fault model and test generation method | Physics | 0 | Active |
| US7793176B2 | Method of increasing path coverage in transition test generation | Physics | 0 | Active |
| US9043180B2 | Reducing power consumption during manufacturing test of an integrated circuit | Physics | 0 | Active |
| US8904329B2 | Systems and methods for single cell product path delay analysis | Physics | 0 | Active |
| US8996282B2 | Fueling systems, methods and apparatus for an internal combustion engine | Emerging Cross-Sectional Technologies | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.