Analyzing multiple induced systematic and statistical layout dependent effects on circuit performance
US8176444B2 · kind B2 · utility
5Cited by
6References
18Claims
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Key dates
| Filing date | Apr 20, 2009 |
| Grant date | May 8, 2012 |
| Priority date | — |
| Expiry date | Dec 30, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2111/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for implementing systematic, variation-aware integrated circuit extraction includes inputting a set of processing conditions to a plurality of variation models, each model corresponding to a separate systematic, parametric variation associated with semiconductor manufacturing of an integrated circuit layout; generating, for each variation model, a netlist update attributable to the associated variation, wherein the netlist update is an update with respect to an original netlist extracted from the integrated circuit layout; and storing the netlist updates generated for each of the processing conditions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.