Replacement spacer for tunnel FETs

US8178400B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Josephine B. Chang · Mahopac, US
• Michael A. Guillorn · Locke, US
• Isaac Lauer · Yorktown Heights, US
• Amlan Majumdar · White Plains, US

Key dates

• Filing date: Sep 28, 2009
• Grant date: May 15, 2012
• Expiry date: Oct 29, 2029

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D12/021

Abstract

A semiconductor fabrication method includes depositing a dummy gate layer onto a substrate, patterning the dummy gate layer, depositing a hardmask layer over the dummy gate layer, patterning the hardmask layer, etching a recess into the substrate, adjacent the dummy gate layer, depositing a semiconductor material into the recess, removing the hardmask layer, depositing replacement spacers onto the dummy gate layer, performing an oxide deposition over the dummy gate layer and replacement spacers, removing the dummy gate and replacement spacers, thereby forming a gate recess in the oxide and depositing a gate stack into the recess.