Method of producing precision vertical and horizontal layers in a vertical semiconductor structure
US8178403B2 · kind B2 · utility
3Cited by
6References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 18, 2007 |
| Grant date | May 15, 2012 |
| Priority date | — |
| Expiry date | Nov 24, 2027 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S977/89
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
The present invention relates to providing layers of different thickness on vertical and horizontal surfaces (15, 20) of a vertical semiconductor device (1). In particular the invention relates to gate electrodes and the formation of precision layers (28) in semiconductor structures comprising a substrate (10) and an elongated structure (5) essentially standing up from the substrate. According to the method of the invention the vertical geometry of the device (1) is utilized in combination with either anisotropic deposition or anisotropic removal of deposited material to form vertical or horizontal layers of very high precision.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.