Methods of manufacturing charge trap-type non-volatile memory devices
US8178408B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 4, 2010 |
| Grant date | May 15, 2012 |
| Priority date | — |
| Expiry date | Feb 13, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/30
Abstract
Some methods are directed to manufacturing charge trap-type non-volatile memory devices. An isolation layer pattern can be formed that extends in a first direction in a substrate. A recess unit is formed in the substrate by recessing an exposed surface of the substrate adjacent to the isolation layer pattern. A tunnel insulating layer and a charge trap layer are sequentially formed on the substrate. The tunnel insulating layer and the charge trap layer are patterned to form an isolated island-shaped tunnel insulating layer pattern and an isolated island-shaped charge trap layer pattern by etching defined regions of the substrate, the isolation layer pattern, the tunnel insulating layer, and the charge trap layer until a top surface of the charge trap layer that is disposed on a bottom surface of the recess unit is aligned with a top surface of the isolation layer pattern. A blocking insulating layer is formed that covers the charge trap layer pattern, the isolation layer pattern, and a defined region of the substrate interposed between the charge trap patterns. A gate electrode pattern is formed on the blocking insulating layer to face the charge trap layer pattern. This manufactur…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.