Method for modifying data more than once in a multi-level cell memory location within a memory array
US8179706B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 19, 2011 |
| Grant date | May 15, 2012 |
| Priority date | — |
| Expiry date | May 19, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for marking a block of multi-level memory cells for performance of a block management function by programming at least one bit in a lower page of the memory cell block such that a first logic state is stored in the at least one bit in the lower page; programming at least one bit in an upper page of the memory cell block such that the first logic state is stored in the at least one bit in the upper page; reprogramming the at least one bit in the upper page such that the at least one bit transitions from the first logic state to a second logic state; identifying the first logic state in the at least one bit of a lower page and the transition of at least one corresponding bit in the upper page from the first logic state to the second logic state; and in response, marking the corresponding memory cell block for performance of a block management function.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.