System and method for hardware acceleration of a software transactional memory
US8180971B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 26, 2010 |
| Grant date | May 15, 2012 |
| Priority date | — |
| Expiry date | Oct 26, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0842
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a transactional memory technique, hardware serves simply to optimize the performance of transactions that are controlled fundamentally by software. The hardware support reduces the overhead of common TM tasks—conflict detection, validation, and data isolation—for common-case bounded transactions. Software control preserves policy flexibility and supports transactions unbounded in space and in time. The hardware includes 1) an alert-on-update mechanism for fast software-controlled conflict detection; and 2) programmable data isolation, allowing potentially conflicting readers and writers to proceed concurrently under software control.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.