System of lanes of processing units receiving instructions via shared memory units for data-parallel or task-parallel operations
US8180998B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 10, 2008 |
| Grant date | May 15, 2012 |
| Priority date | — |
| Expiry date | Jul 24, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/17362
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for performing data-parallel operations and task-parallel operations. A first switch fabric node (SFN) includes first and second lane processing engines (LPEs). The first LPE includes a first set of lane processing units (LPUs) configured to perform data-parallel operations, where each LPU performs a set of operations, and each LPU uses a different set of data for the set of operations, and each LPU within the first set of LPUs uses a different set of data for the set of operations. The second LPE includes a second set of LPUs configured to perform task-parallel operations, where each LPU performs a different set of operations. A processing control engine (PCE) is configured to distribute instructions and data to the first LPE and the second LPE. Advantageously, data parallel operations and task parallel operations are able to be performed on the same processor simultaneously.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.