Error correcting Viterbi decoder
US8181098B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 11, 2008 |
| Grant date | May 15, 2012 |
| Priority date | — |
| Expiry date | Mar 16, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6362
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Methods and corresponding systems in a Viterbi decoder include computing a maximum likelihood (ML) path in a Viterbi trellis in response to executing a first Viterbi algorithm. Thereafter, one or more merge points are selected on the ML path in a second Viterbi algorithm, wherein the merge points each have a path metric difference, which is a difference between an ML path metric at the merge point and a non-surviving path metric at the merge point. Merge points are selected based upon relative path metric differences associated with nodes on the ML path. Next, alternate paths in the Viterbi trellis are computed based on the ML path with alternate paths substituted at corresponding merge points. A passing decoded bit sequence is output in response to passing an error check, wherein the passing decoded bit sequence is associated with one of the one or more alternate paths.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.