Patent · US Active

Multi-priority placement for configuring programmable logic devices

US8181139B1 · kind B1 · utility

8Cited by

7References

10Claims

0Family size

Assignee

Lattice Semiconductor Corporation · US

Inventors

Xiaotao Chen · Jalan Pedongkelan, US
Eric Ting · Los Altos, US
Ruofan Xu · Allentown, US
Yanhua Yi · Allentown, US
Jun Zhao · Mianyang, CN

Key dates

Filing date	Dec 22, 2008
Grant date	May 15, 2012
Priority date	—
Expiry date	Nov 2, 2029

Classification

Technology area (CPC G)Physics
CPC primaryG06F30/392
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

In one embodiment of the invention, a computer-implemented method of configuring a programmable logic device (PLD) includes placing logical functions within logical resources of the PLD to implement a desired netlist; swapping the logical function of at least one logical resource with the logical function of at least one other logical resource within the PLD; and evaluating whether to accept or reject the swap using a simulated annealing process that calculates at least three cost function values based upon routing priority groups, timing priority groups, and a timing critical group.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.