T-coil network design for improved bandwidth and electrostatic discharge immunity
US8181140B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 9, 2009 |
| Grant date | May 15, 2012 |
| Priority date | — |
| Expiry date | Jul 27, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/017545
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of generating a circuit design comprising a T-coil network includes determining inductance for inductors and a parasitic bridge capacitance of the T-coil network. The parasitic bridge capacitance is compared with a load capacitance metric that depends upon parasitic capacitance of a load coupled to an output of the T-coil network. An amount of electrostatic discharge (ESD) protection of the circuit design that is coupled to the output of the T-coil network and/or a parameter of the inductors of the T-coil network is selectively adjusted according to the comparison. The circuit design, which can specify inductance of the inductors, the amount of ESD protection, and/or the width of windings of the inductors, is outputted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.