Patent · US Active

Method for identifying and implementing flexible logic block logic for easy engineering changes

US8181148B2 · kind B2 · utility

1Cited by

10References

17Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Robert D. Herzl · South Burlington, US
Robert S. Horton · Colchester, US
Kenneth A. Lauricella · Colchester, US
David W. Milton · Underhill, US
Clarence R. Ogilvie · Waterbury, US
Paul M. Schanely · South Burlington, US
Nitin Sharma · Kenosha, US
Tad J. Wilder · South Hero, US
Charles B. Winn · Colchester, US

Key dates

Filing date	Jan 15, 2008
Grant date	May 15, 2012
Priority date	—
Expiry date	Feb 18, 2029

Classification

Technology area (CPC G)Physics
CPC primaryG06F30/30
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A chip design methodology. The methodology includes identifying engineering changeable logic, and replacing the identified engineering changeable logic with flexible logic blocks (FLB).

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.