Method for bonding wafers to produce stacked integrated circuits
US8183127B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 24, 2010 |
| Grant date | May 22, 2012 |
| Priority date | — |
| Expiry date | May 24, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/351
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A basic building block for wafer scale stacked integrated circuits is disclosed. The building block includes an integrated circuit device having an integrated circuit substrate having a circuit layer sandwiched between a buffer layer and a dielectric layer. The dielectric layer has a top side and a bottom side, the bottom side being in contact with the circuit layer. The top surface of the dielectric layer includes a plurality of pads. Each pad extends above the top surface by a predetermined distance. The pads have dimensions that reduce irregularities in the top surface of the pads. In addition, the pads are arranged in a manner to promote planarization of the surface of the wafer via CMP.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.