Layouts for the monolithic integration of CMOS and deposited photonic active layers
US8183516B2 · kind B2 · utility
7Cited by
2References
26Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 28, 2005 |
| Grant date | May 22, 2012 |
| Priority date | — |
| Expiry date | Jun 9, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10H29/142
Abstract
Several detailed layout designs are disclosed, for the monolithic integration of avalanche devices in large arrays, that can be operated as Avalanche Photo-Diodes (APDs) or Avalanche Light Emitting Diodes (ALEDs) depending only on the applied bias conditions, which can be software-controlled from peripheral circuitry. If the deposited films have direct bandgaps, then the devices can emit light even in the absence of avalanche operation. In particular, the layouts according to the invention comprise a sensor/emitter matrix achieved through the replication of basic Pixel/Lixel cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.