Spin transistor using N-type and P-type double carrier supply layer structure
US8183611B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 18, 2010 |
| Grant date | May 22, 2012 |
| Priority date | — |
| Expiry date | Nov 20, 2030 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/902
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A spin transistor that includes: a semiconductor substrate including an upper cladding layer and a lower cladding layer, and a channel layer interposed between the upper and lower cladding layers; a ferromagnetic source and a ferromagnetic drain formed on the semiconductor substrate and spaced from each other in a length direction of the channel layer; and a gate electrode formed on the semiconductor substrate between the source and the drain and having applied a gate voltage thereto to control a spin precession of an electron passing through the channel layer, wherein the semiconductor substrate includes a first carrier supply layer of a first conductivity type disposed below the lower cladding layer and supplying carriers to the channel layer, and a second carrier supply layer of a second conductivity type opposite to the first conductivity type formed on the upper cladding layer and supplying the carriers to the channel layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.