Semiconductor structure and method of fabricating the semiconductor structure
US8183628B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 12, 2010 |
| Grant date | May 22, 2012 |
| Priority date | — |
| Expiry date | Aug 15, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0172
Abstract
In contrast to a conventional planar CMOS technique in design and fabrication for a field-effect transistor (FET), the present invention provides an SGT CMOS device formed on a conventional substrate using various crystal planes in association with a channel type and a pillar shape of an FET, without a need for a complicated device fabrication process. Further, differently from a design technique of changing a surface orientation in each planar FET, the present invention is designed to change a surface orientation in each SGT to achieve improvement in carrier mobility. Thus, a plurality of SGTs having various crystal planes can be formed on a common substrate to achieve a plurality of different carrier mobilities so as to obtain desired performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.