Dual port static random access memory cell layout
US8183639B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 7, 2010 |
| Grant date | May 22, 2012 |
| Priority date | — |
| Expiry date | Oct 7, 2030 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/903
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dual port static random access memory cell has pull-down transistors, pull-up transistors, and pass transistors. A first active region has a first pull-down transistor coupled to a true data node, a second pull-down transistor coupled to a complementary data node; a first pass transistor coupled to the true data node, and a second pass transistor coupled to the complementary data node. A second active region has the same size and shape as the first active region and has a third pull-down transistor coupled in parallel to the first-pull down transistor, a fourth pull-down transistor coupled in parallel to the second pull-down transistor; a third pass transistor coupled to the true data node, and a fourth pass transistor coupled to the complementary data node. A first pull-up transistor and a second pull-up transistor are located between the first and second active regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.