High voltage tolerance of external pad connected MOS in power-off mode
US8183911B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 19, 2009 |
| Grant date | May 22, 2012 |
| Priority date | — |
| Expiry date | Jan 21, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/0822
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes a number of pads. The integrated circuit further includes a cascode transistor having an open drain connection to a first one of the pads. A bias generator circuit is included in the integrated circuit. The bias generator circuit has an output connected to a gate terminal of the cascode transistor. In a first mode of operation, the bias generator outputs a bias signal that is derived from an integrated circuit supply voltage present at a second one of the pads. However, in a second mode of operation provided when the integrated circuit supply voltage is not present, the bias generator generates the bias signal derived from a voltage present at the first one of the pads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.