Semiconductor apparatus
US8184463B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 13, 2009 |
| Grant date | May 22, 2012 |
| Priority date | — |
| Expiry date | Sep 8, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The need for mediation operation is eliminated by adoption of a connection topology in which a circuit for executing one transmission (TR—00T), and a circuit for executing a plurality of receptions (TR—10R, TR—20R, TR—30R) are connected to one penetration-electrode group (for example, TSVGL—0). In order to implement the connection topology even in the case of piling up a plurality of LSIs one after another, in particular, a programmable memory element for designating respective penetration-electrode ports for use in transmit, or for us in receive, and address allocation of the respective penetration-electrode ports is mounted in stacked LSIs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.