Asymmetric SRAM cell with split transistors on the strong side
US8184474B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 19, 2010 |
| Grant date | May 22, 2012 |
| Priority date | — |
| Expiry date | Jan 26, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/412
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit containing an SRAM cell array in which each SRAM cell includes an auxiliary NMOS driver or PMOS load transistor plus a bit-side passgate transistor and a bit-bar-side passgate transistor. An integrated circuit containing an SRAM cell array in which each SRAM cell includes an auxiliary PMOS driver or NMOS load transistor plus a bit-side passgate transistor and a bit-bar-side passgate transistor. A process of operating an integrated circuit containing an SRAM cell array in which each SRAM cell includes an auxiliary NMOS driver or PMOS load transistor plus a bit-side passgate transistor and a bit-bar-side passgate transistor. A process of operating an integrated circuit containing an SRAM cell array in which each SRAM cell includes an auxiliary PMOS driver or NMOS load transistor plus a bit-side passgate transistor and a bit-bar-side passgate transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.