Tri-state driver circuits having automatic high-impedance enabling
US8184492B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 9, 2009 |
| Grant date | May 22, 2012 |
| Priority date | — |
| Expiry date | Jun 8, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/09429
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Memories, driver circuits, and methods for generating an output signal in response to an input signal. One such driver circuit includes an input stage and an output stage. The input stage receives the input signal and provides a delayed input signal having a delay relative to the input signal. The output stage receives the delayed input signal and further receives the complement of the input signal. The output stage couples an output node to a first voltage in response to a complement of the input signal having a first logic level and couples the output to a second voltage in response to the complement of the input signal having a second logic level. The output stage further decouples the output from the first or second voltage in response to receiving the delayed input signal to provide a high-impedance at the output node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.