High-radix interprocessor communications system and method
US8184626B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jan 12, 2009 |
| Grant date | May 22, 2012 |
| Priority date | — |
| Expiry date | Feb 18, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/15
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A high-radix interprocessor communications system and method having a plurality of processor nodes, a plurality of first routers and a plurality of second routers. Each first router is connected to a processor node and to two or more second routers. Each first router includes input ports, output ports, row busses, columns channels and a plurality of subswitches arranged in a n x p matrix. Each row bus receives data from one of the plurality of input ports and distributes the data to two or more of the plurality of subswitches. Each column distributes data from one or more subswitches to one or more output ports. Each row bus includes a route selector, wherein the route selector includes a routing table which selects an output port for each packet and which routes the packet through one of the row busses to the selected output port.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.