Secure computing device with monotonic counter and method therefor
US8184812B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 3, 2009 |
| Grant date | May 22, 2012 |
| Priority date | — |
| Expiry date | Aug 17, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F21/72
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A secure computing device (14) includes a secure processing section (30) having a tamper detection circuit (58) and a monotonic counter (68). The tamper detection circuit (58) detects an event which suggests that the trust associated with the secure processing section (30) may have been compromised. When such an event is detected, a security breach is declared and trusted software (38) is disabled. After a security breach is declared, the monotonic counter (68) may be reclaimed. The monotonic counter (68) provides a monotonic count value (70) that includes an LSB portion (80) and an MSB portion (82). The LSB portion (80) is obtained from a binary counter (72). The MSB portion (82) is obtained from a register (84) of independent one-time-programmable bits. The monotonic counter (68) is reclaimed by programming one of the one-time programmable bits to guarantee that future counting of the monotonic counter will be monotonic relative to all past counting.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.