Low pin interface testing module
US8185338B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 24, 2008 |
| Grant date | May 22, 2012 |
| Priority date | — |
| Expiry date | Oct 25, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318572
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A low pin interface module is provided for testing an integrated circuit. The interface module includes an input-output module, a controlling module, a processing module and a storage module specific to the integrated circuit to be tested. The interface module reduces the required number of hardware pins in the integrated circuit for a standalone testing without limiting the integrated circuit testing features. A methodology and a control mechanism achieved with the interface module can be used for the standalone testing of any integrated circuit without using a Joint European Test Action Group test logic interface JTAG implemented following the IEEE Standard 1149.1-1990. The interface module is not limited by a particular debugging platform and allows access to all test features in the integrated circuit with a reduced number of hardware pins and thereby leading to enhanced testing speeds on a tester in parallel and a shorter time-to-a market cycle and a lower development cost.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.