Enabling speculative state information in a cache coherency protocol
US8185700B2 · kind B2 · utility
16Cited by
4References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 30, 2006 |
| Grant date | May 22, 2012 |
| Priority date | — |
| Expiry date | May 18, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/507
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, the present invention includes a method for receiving a bus message in a first cache corresponding to a speculative access to a portion of a second cache by a second thread, and dynamically determining in the first cache if an inter-thread dependency exists between the second thread and a first thread associated with the first cache with respect to the portion. Other embodiments are described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.