Processor block ASIC core for embedding in an integrated circuit
US8185720B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 5, 2008 |
| Grant date | May 22, 2012 |
| Priority date | — |
| Expiry date | Apr 14, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/7889
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A hardwired core is embedded in an integrated circuit having programmable circuitry. The hardwired core has a microprocessor; a crossbar interconnect coupled to processor local buses of the microprocessor; and a memory controller interface coupled to the crossbar interconnect. The crossbar interconnect provides pipelines for coupling the hardwired core to the programmable circuitry. The microprocessor, the crossbar interconnect, and the memory controller interface are all capable of operating at a first frequency of operation, and the memory controller interface is further capable of being set to operate at a second frequency of operation having an integer ratio with respect to the first frequency of operation. The crossbar interconnect is configured to direct transactions initiated by the microprocessor to the memory controller interface for accessing one or more memory devices coupled to the memory controller interface via a memory controller. Additional or other interfaces may be coupled to the crossbar interconnect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.