Method for data processing using a multi-tiered full-graph interconnect architecture
US8185896B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 27, 2007 |
| Grant date | May 22, 2012 |
| Priority date | — |
| Expiry date | Jun 2, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2209/5012
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method is provided for implementing a multi-tiered full-graph interconnect architecture. In order to implement a multi-tiered full-graph interconnect architecture, a plurality of processors are coupled to one another to create a plurality of processor books. The plurality of processor books are coupled together to create a plurality of supernodes. Then, the plurality of supernodes are coupled together to create the multi-tiered full-graph interconnect architecture. Data is then transmitted from one processor to another within the multi-tiered full-graph interconnect architecture based on an addressing scheme that specifies at least a supernode and a processor book associated with a target processor to which the data is to be transmitted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.