Fabricating process of structure with embedded circuit
US8187478B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 16, 2008 |
| Grant date | May 29, 2012 |
| Priority date | — |
| Expiry date | Mar 17, 2031 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49155
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A fabricating process of a structure with an embedded circuit is described as follows. Firstly, a substrate having an upper surface and a lower surface opposite to the upper surface is provided. Afterward, a dielectric layer is formed on the upper surface of the substrate. Next, a plating-resistant layer is formed on the dielectric layer. Then, the plating-resistant layer and the dielectric layer are patterned for forming an recess pattern on the dielectric layer. Subsequently, a conductive base layer is formed in the recess pattern by using a chemical method, and the plating-resistant layer is exposed by the conductive base layer. After that, the plating-resistant layer is removed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.