Structure and layout of a FET prime cell
US8187930B2 · kind B2 · utility
1Cited by
9References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 25, 2007 |
| Grant date | May 29, 2012 |
| Priority date | — |
| Expiry date | Nov 4, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/257
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Method of making a semiconductor device that includes forming a source and a drain in a substrate, forming a gate on the substrate between the source and drain, forming a substrate contact in electrical contact with the source, and forming an electrical contact to the source, drain and gate, and the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.