Creating integrated circuit capacitance from gate array structures

US8188516B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Anthony Correale, Jr. · Raleigh, US
• Benjamin J. Bowers · Cary, US
• Douglass T. Lamb · Cary, US
• Nishith Rohatgi · Raleigh, US

Key dates

• Filing date: Mar 4, 2010
• Grant date: May 29, 2012
• Expiry date: Oct 28, 2030

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D1/68

Abstract

Techniques for using gate arrays to create capacitive structures within an integrated circuit are disclosed. Embodiments comprise placing a gate array of P-type field effect transistors (P-fets) and N-type field effect transistors (N-fets) in an integrated circuit design, coupling drains and sources for one or more P-fets and gates for one or more N-fets to a power supply ground, and coupling gates for the one or more P-fets and the drains and sources for one or more N-fets to a positive voltage of the power supply. In some embodiments, source-to-drain leakage current for capacitive apparatuses of P-fets and N-fets are minimized by biasing one or more P-fets and one or more N-fets to the positive voltage and the ground, respectively. In other embodiments, the capacitive structures may be implemented using fusible elements to isolate the capacitive structures in case of shorts.